Method for fabricating semiconductor device
US7122467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.