Power-up circuit in semiconductor memory device
US7123062B2 · kind B2 · utility
9Cited by
13References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Feb 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/468
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A power-up circuit of a semiconductor memory device includes a power supply voltage level follower unit for providing a bias voltage which is linearly varied according to variation of a power supply voltage, a power supply voltage detection unit for detecting the variation of the power supply voltage to a predetermined critical voltage level in response to the bias voltage, and a reset prevention unit for canceling variation of the detection signal due to a power drop by delaying level transition of the detection signal according to decrease of the power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.