Method and apparatus for achieving low power consumption during power down
US7123522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage buses provide power throughout the semiconductor chip. In a deep power down mode, grounding devices may be utilized to ground the internal voltage buses. With the internal voltage buses grounded, the outputs of the level shifters, which are control signals, may need to be forced into specific states. Through the use of the grounding devices and level shifters, leakage may be reduced and latch-up conditions may be reduced. As a result, the operation of the semiconductor chip may be enhanced because the problems associated with grounding the internal voltage buses may be diminished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.