Integration of multiple gate dielectrics by surface protection

US7126172B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Sangwoo Lim · Austin, US
• Laegu Kang · Hopewell Junction, US
• Geoffrey Yeap · San Diego, US

Key dates

• Filing date: Oct 12, 2004
• Grant date: Oct 24, 2006
• Expiry date: Oct 13, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer (211) within the first etched region; (e) depositing and patterning a second layer of photoresist (213) on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer (215) within the second etched region.