Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7129567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Aug 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed therethrough. At least one seed layer may be formed, patterned, and a metal may be deposited thereon to form a plurality of conductive elements. Alternatively, the at least one through-hole may be substantially filled with a dielectric material and a plurality of smaller through-holes may be formed therein and then filled with conductive material to form a plurality of conductive elements. Alternatively, at least one cavity may be formed into a substrate and a plurality of conductive nanotubes or other protruding structures may be formed therein. The substrate may be thinned to form at least one through-hole and a plurality of laterally separated conductive elements extending therethrough. Semiconductor dice, substrates, as well as multichip modules having dice including multiconductor vias, systems including same, and methods of manufacture are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.