Multi-level ONO flash program algorithm for threshold width control
US7130210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2005 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Jan 22, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. T…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.