Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage

US7132318B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Henry A. Bonges, III · Colchester, US
• David L. Harmon · South Burlington, US
• Terence B. Hook · Jericho, US
• Wing L. Lai · Williston, US

Key dates

• Filing date: Dec 4, 2004
• Grant date: Nov 7, 2006
• Expiry date: Jun 23, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.