Transistor, memory cell array and method of manufacturing a transistor

US7132333B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Till Schloesser · Dresden, DE
• Rolf Weis · Dresden, DE
• Ulrike Gruening-von Schwerin · Munich, DE

Key dates

• Filing date: Sep 10, 2004
• Grant date: Nov 7, 2006
• Expiry date: Sep 10, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.