Charge-trapping memory device and method of production

US7132337B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Stefan Jakschik · Kessel-Lo, BE
• Matthias Goldbach · Dresden, DE
• Thomas Mikolajick · Birkenfeld, DE
• Thomas Hecht · Dresden, DE

Key dates

• Filing date: Dec 20, 2004
• Grant date: Nov 7, 2006
• Expiry date: Dec 20, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.