Method and apparatus to reduce storage node disturbance in ferroelectric memory
US7133304B2 · kind B2 · utility
24Cited by
15References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 22, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.