System and method for handling exceptional instructions in a trace cache based processor
US7133969B2 · kind B2 · utility
27Cited by
15References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.