Cache memory system including a cache memory employing a tag including associated touch bits
US7133975B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Nov 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system including a cache memory employing a tag including associated touch bits. The system includes a first cache memory subsystem having a first cache storage and a second cache memory subsystem including a second cache storage. The first cache storage may store a first plurality of cache lines of data. The second cache storage may store a second plurality of cache lines of data. Further the second cache memory subsystem includes a tag storage which may store a plurality of tags each corresponding to a respective cache line of the second plurality of cache lines. In addition, each of said plurality of tags includes an associated bit indicative of whether a copy of the corresponding respective cache line is stored within the first cache memory subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.