Method and apparatus for efficient register-transfer level (RTL) power estimation
US7134100B2 · kind B2 · utility
36Cited by
3References
27Claims
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Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for accelerating power estimation for a circuit comprising generating an RTL description of the circuit. A power model enhanced RTL description of the circuit is generated. A simulator is selected. The power model enhanced RTL description is modified to make it more friendly to the simulator. The simulator is run to estimate the power consumed by the circuit. Techniques using delayed computation and partitioned sampling are also provided. Power estimation systems using the above techniques area also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.