Vertical DRAM and fabrication method thereof
US7135731B2 · kind B2 · utility
4Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
Abstract
A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.