Robust power semiconductor package
US7135761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Feb 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor package, including a leadframe having at least one first terminal, a second terminal and a third terminal. The package also includes a semiconductor power die having a bottom surface defining a first current carrying electrode and a top surface on which a first metalized region defining a second current carrying electrode and a second metalized region defining a control electrode are disposed, the bottom surface being coupled to the leadframe such that the first terminal is electrically connected to the first current carrying electrode. A clip is also coupled to the first metalized region defining the second current carrying electrode and to the second terminal such that it is electrically coupled to the second current carrying electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.