Method and apparatus for performing density-biased buffer insertion in an integrated circuit design
US7137081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Oct 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer program product for performing density biased buffer insertion in an integrated circuit design are provided. A tiled Steiner tree topology map is used in which density values are associated with each tile in the map. A directed acyclic graph (DAG) is created over an initial set of potential candidate points. A subset of the candidate points is selected by associating costs with each tile, and with each path or edge, to each tile. The total costs associated with placement of a buffer at a position within each tile are calculated. The lowest cost tile is then selected as a candidate position for buffer insertion. This process is then repeated to obtain an asymmetrically distributed set of candidate buffer insertion points between a source and a sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.