Replacement gate with TERA cap
US7138308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Mar 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
Abstract
A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.