Production method of III nitride compound semiconductor and III nitride compound semiconductor element
US7141444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2001 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Mar 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02647
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate. The layer serving as a nucleus of ELO may be doped with indium (In) having an atomic radius greater than that of gallium (Ga) serving as a predominant element. The first semiconductor layer may be a multi-component layer containing a plurality of numbers …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.