Apparatus and method to reduce undesirable effects caused by a fault in a memory device
US7142446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Aug 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.