Positive gate stress during erase to improve retention in multi-level, non-volatile flash memory
US7142455B1 · kind B1 · utility
9Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jun 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new method for improving the accuracy of read-write operations in a multi-level flash memory cell is disclosed. The method reduces the read margin disturbance caused by the accumulation of holes at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the cell by applying a positive stress to the word line after a program-erase cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.