Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses
US7142477B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases. This will essentially reduce the cycle time between a read and write memory access, and proves useful when maximizing the data throughput across the data bus when implementing double data rate (QDR) mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.