Methods of routing programmable logic devices to minimize programming time
US7143384B1 · kind B1 · utility
4Cited by
8References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 18, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jan 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.