Magnetoresistive random access memory device structures and methods for fabricating the same
US7144744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2004 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.