Method of manufacturing semiconductor device having trench isolation
US7144764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2004 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.