Semiconductor device
US7145205B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2003 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Dec 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a semiconductor substrate having two types of active regions that are a PMOS region and an NMOS region separated from each other in plan view by a PN separation film; and a dual-gate electrode extending linearly across the PMOS region, the PN separation film and the NMOS region collectively on an upper side of the semiconductor substrate. The dual-gate electrode includes a P-type portion, an N-type portion and a PN junction positioned therebetween. The PN junction includes a silicide region. The silicide region is apart from both the PMOS region and the NMOS region and formed within the area of the PN separation film in plan view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.