Method and circuits for localizing defective interconnect resources in programmable logic devices
US7145344B2 · kind B2 · utility
4Cited by
25References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2003 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Apr 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318519
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.