Digital delay device, digital oscillator clock signal generator and memory interface
US7148728B2 · kind B2 · utility
3Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Nov 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digitally controlled delay device, including a plurality of fine delay elements and a plurality of coarse delay elements, capable of delaying a signal generated by the device, by a fine or coarse delay respectively, the fine delay elements having delay times of between 60 and 170% of the mean of the fine delays and the sum of the fine delay times being greater than or equal to at least one coarse delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.