Biasing circuit for use in a non-volatile memory device
US7149132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Jan 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to receive a supply voltage, a second input coupled to receive a reference voltage, and an output coupled to one of the row decoder and the column decoder to supply the first biasing voltage. A second voltage booster has a first input coupled to receive the supply voltage, a second input coupled to the output of the first voltage booster to receive the first biasing voltage, and an output coupled to the other of the row decoder and the column decoder to supply the second biasing voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.