Data reordering processor and method for use in an active memory device
US7149875B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2003 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Dec 6, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7821
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. The active memory device includes a vector processing and re-ordering system coupled to the array control unit and the memory device. The vector processing and re-ordering system re-orders data received from the memory device into a vector of contiguous data, process the data in accordance with an instruction received from the array control unit to provide results data, and passes the results data to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.