Method and apparatus for transistor sidewall salicidation
US7151018B1 · kind B1 · utility
8Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2004 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Nov 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a transistor is provided. The transistor has a substrate with an insulator on the substrate. A structure on the insulator having a structure sidewall is provided with spacers covering a portion of the structure sidewall. An exposed portion of the structure sidewall is activated, and a conformal layer of metal or metal containing material is deposited on the exposed portion of the structure sidewall. The metal or metal containing material is annealed to diffuse into the exposed portion of the structure sidewall to form a salicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.