Technique for forming a gate electrode by using a hard mask
US7151055B2 · kind B2 · utility
8Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2004 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The anisotropic etch process for forming circuit elements such as a gate electrode is accomplished by using a hard mask instead of a resist feature, thereby avoiding a complex resist trim process when critical dimensions are required, which are well below the resolution of the involved photolithography. Moreover, the critical dimension may be adjusted by means of a deposition process rather than by a resist trim process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.