MOS transistor and method of manufacture
US7151059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2004 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jan 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.