Self-aligned, silicided, trench-based, DRAM/EDRAM processes with improved retention
US7153737B2 · kind B2 · utility
9Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jan 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.