Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US7153763B2 · kind B2 · utility
109Cited by
40References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.