Encoder and decoder circuits for dynamic bus
US7154300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Nov 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.