Memory device including barrier layer for improved switching speed and data retention
US7154769B2 · kind B2 · utility
12Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jun 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/51
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present memory device includes a first electrode, a passive layer on and in contact with the first electrode, the passive layer including copper sulfide, a barrier layer on and in contact with the passive layer, an active layer on and in contact with the barrier layer, and a second electrode on and in contact with the active layer. The inclusion of the barrier layer in this environment increases switching speed of the memory device, while also improving data retention thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.