Non-volatile memory cell using high-k material inter-gate programming
US7154779B2 · kind B2 · utility
80Cited by
29References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Apr 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.