Digital signal processing for real time classification of failure bitmaps in integrated circuit technology development
US7155652B1 · kind B1 · utility
2Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Oct 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for processing tester information is provided having a system-under-test. A pattern is written to the system-under-test, and a pattern is read therefrom. The pattern written is then compared to the pattern read from the system-under-test. The signal from the comparison is processed, and the signal from the signal processing is then analyzed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.