Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7157378B2 · kind B2 · utility
85Cited by
26References
20Claims
0Family size
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Key dates
| Filing date | Jul 6, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Jul 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.