Memory with robust data sensing and method for sensing data
US7158432B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2005 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Sep 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory (100) includes first (116) and second (118) sense amplifiers, a first logic gate (120), a first three-state driver (130), and a latch (180). The first sense amplifier (116) is coupled to a first local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the first local data line. The second sense amplifier (118) is coupled to a second local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the second local data line. The first three-state driver (130) has a data input terminal coupled to the output terminal of the first logic gate (120), a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line. The latch (180) has an input/output terminal coupled to the global data line (170).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.