Memory chip with test logic taking into consideration the address of a redundant word line and method for testing a memory chip
US7159156B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Jan 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word lines that, in the case of a memory cell recognized as defective, are used instead of the word line regularly activated. The scrambler unit is connected to the repair unit and, thus, receives from the repair unit information on whether the redundant word line replacing a defective word line drives transistors of memory cells that can be connected to true bit lines or to complementary bit lines. As such, the scrambler unit can take the information as to whether a true bit line or a complementary bit line is driven through the spare word line into consideration when performing the test procedure. This provides for a more efficient performance of the test procedure. Also provided is a method for testing memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.