Etch back process approach in dual source plasma reactors
US7160813B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jun 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32137
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for removing a polysilicon layer from a semiconductor wafer, in which a downstream plasma source is used first to planarize the wafer, removing contours in the polysilicon layer caused by deposition over lithographic features, such as via holes. The planarizing process is followed by exposure to a plasma made by a direct, radio frequency plasma source, which may be in combination with the downstream plasma source, to perform the bulk etching of the polysilicon. The invention can produce planar surface topography after the top layer of the film is removed, in which the residual recess height of the polysilicon plug filling a via hole is less than about about 10 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.