Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof

US7161199B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Jian Chen · Austin, US
• Michael A. Mendicino · Austin, US
• Vance H. Adams · Austin, US
• Choh Fei Yeap · San Diego, US
• Venkat R. Kolagunta · Austin, US

Key dates

• Filing date: Aug 24, 2004
• Grant date: Jan 9, 2007
• Expiry date: Aug 24, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.