SRAM having improved cell stability and method therefor
US7161827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2005 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Feb 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM (14) includes a SRAM cell (26), the cell (26) includes a first storage node (N1), a second storage node (N2), and a cross coupled latch (40) including a first primary source current path to the first storage node, a first primary sink current path to the first storage node, a second primary source current path to the second storage node, a second primary sink current path to the second storage node, a fifth primary current path to the first storage node, and a sixth primary current path to the second storage node. During standby and/or a read operation of the SRAM cell (26), one of the fifth primary current path and the sixth primary current path is conductive. During a write operation, the fifth primary current path and the sixth primary current path are non-conductive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.