Edge seal for a semiconductor device
US7163883B2 · kind B2 · utility
16Cited by
14References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2003 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.