Plating method for circuitized substrates
US7169313B2 · kind B2 · utility
4Cited by
20References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of plating a circuit pattern on a substrate to produce a circuitized substrate (e.g., a printed circuit board) in which a dual step metallurgy application process is used in combination with a dual step photo-resist removal process. Thru-holes are also possible, albeit not required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.