Process and lead frame for making leadless semiconductor packages
US7169651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Apr 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.