Method of manufacturing a split-gate flash memory device
US7169668B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Feb 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area. Afterward, a composite dielectric layer is formed on the substrate and covers the conductive lines. Finally, a plurality of word lines are formed on the composite dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.