Dual damascene trench formation to avoid low-K dielectric damage
US7169701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Mar 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.