Chip structure and stacked-chip package
US7170160B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Dec 12, 2005 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Dec 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip structure including a chip, a first passivation layer, a redistribution layer and a second passivation layer is provided. The chip has a wire bonding area adjacent to one side or two sides adjacent to each other of the chip, wherein the chip has multiple first bonding pads disposed inside the wire bonding area and multiple second pads disposed outside the wire bonding area. The first passivation layer disposed on the chip has multiple first openings by which the first and the second bonding pads are exposed. The redistribution layer is disposed on the first passivation layer and extended from the second bonding pads to the wire bonding area. The redistribution layer has multiple third bonding pads located inside the wire bonding area. The second passivation layer disposed over the redistribution layer has multiple second openings by which the first and the third bonding pads are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.